Method and apparatus for testing a storage interface
US7047460B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | May 16, 2006 |
| Priority date | — |
| Expiry date | Mar 21, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tester or method of testing a mass storage interface queues error functions for simulation responsive to condition criteria of such storage simulation. Such bridge-chip tester may comprise ATA registers to receive data from an ATA or ATAPI-type interface. A main access emulator may emulate data storage processes responsive to commands of a command register of the ATA registers. A test controller may be operable to load a queue with predetermined error functions to be emulated by the tester. The queue may release error functions of the queue for emulation responsive to data of at least one of the command register and the emulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.