Method for manufacturing vias between conductive patterns utilizing etching mask patterns formed on the conductive patterns
US7049225B2 · kind B2 · utility
1Cited by
10References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 23, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Mar 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a manufacture of a semiconductor device, spacers are formed on sidewalls of structures including conductive patterns and insulation patterns. The insulation patterns are at least four times thinner than the conductive patterns. After gaps between the structures are filled with a first insulation film, etch stop film patterns having a width which is wider than that of the structures are formed on the structures. A second insulation film is formed to cover the resultant structures without voids between the structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.