Apparatus and method for high frequency state machine divider with low power consumption
US7049864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Aug 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.