Digital delaying device
US7049874B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jun 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M2201/14
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital delaying device for delaying an input signal includes a ring oscillator, a calibration unit, and at least one delay number calculation unit and delay channel. The ring oscillator includes loop-connected delay cells for outputting an oscillation clock. The calibration unit receives a reference clock and the oscillation clock and calculates a pulse number of the oscillation clock corresponding to each reference clock period. The pulse number serves as a period reference pulse number. The calculation unit receives the pulse number and a signal delay value, calculates a signal delay number corresponding to the signal delay value according to the pulse number, and outputs a selection signal. The delay channel includes a multiplexer and cascaded delay cells, which receives an input signal and generates delay signals with different delay timings. The multiplexer selects and outputs one of the delay signals as an output signal according to the selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.