3-D rendering texture caching scheme
US7050063B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2000 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Feb 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.