Method and apparatus for multiple row caches per bank
US7050351B2 · kind B2 · utility
12Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jan 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to read the contents of that at least one row through a read operation causing the data to read from the row of sense amplifiers versus from the row of memory cells, directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.