Wire speed reassembly of data frames
US7050437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2001 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Oct 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network interface device includes receive logic, which is coupled to receive from a network a sequence of data packets, each packet including respective header data. A protocol processor is coupled to read and process the header data so as to identify a group of the received packets that contain respective fragments of a data frame, the fragments having a fragment order within the data frame. Host interface logic is coupled to a host memory accessible by a host processor, and is controlled by the protocol processor so as to allocate space for the data frame in the host memory, and to reassemble the fragments of the data frame in the fragment order in the space allocated in the host memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.