Hardware accelerated compression
US7051126B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3084
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compression system is arranged to use software and/or hardware accelerated compression techniques to increase compression speeds and enhance overall data throughput. A logic circuit is arranged to: receive a data stream from a flow control processor, buffer the data stream, select a hardware compressor (e.g., an ASIC), and forward the data to the selected hardware compressor. Each hardware compressor performs compression on the data (e.g., LZ77), and sends the compressed data back to the logic circuit. The logic circuit receives the compressed data, converts the data to another compressed format (e.g., GZIP), and forwards the converted and compressed data back to the flow control processor. History associated with the data stream can be stored in memory by the flow control processor, or in the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.