Method and system for providing a multi-channel interleaver/deinterleaver using SDRAM
US7051171B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.