Mechanism for reducing power consumption of a transmitter/receiver circuit
US7051220B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism that reduces power consumption of a transmitter/receiver circuit in a wireless device. The transmitter/receiver circuit is powered down to a reduced-power state after transmitting a message. The reduced-power state is too low to be able to transmit or receive information. Round trip statistics regarding how low it typically takes to receive a response to the message are then used to determine when to power up the transmitter/receiver circuit to the extent that it could receive the response. Accordingly, by being powered up for only a window of time in which the receipt of the response would likely occur, the transmitter/receiver circuit consumes less power while still likely receiving the response. The window of time may be adjusted as appropriate for the importance of the information, the performance of the specific wireless network, and the sensitivity of the wireless network to not receiving the response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.