Method and apparatus for configuring a clock timing feedback path
US7051224B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jan 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and apparatus for configuring a timing feedback path in a semiconductor device. The apparatus includes an oscillator adapted to provide a reference clock signal. The apparatus further includes at least one buffer layer adapted to receive the reference clock signal and provide a delayed clock signal, a selector adapted to select one of the delayed clock signal and the reference clock signal, and a device adapted to provide an output clock signal such that the selected one of the delayed clock signal and the reference clock signal is substantially in phase with the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.