Method and system for using machine-architecture support to distinguish function and routine return values
US7051238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.