Signal compensation circuit of a bus
US7051241B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal compensation circuit of a bus is disclosed in the present invention, wherein the amplitude of a surge is obtained by inputting a test pattern into the bus and comparing a reference voltage and a peak-value signal filtered out from the bus. For continual correction of the damping resistance, the test pattern can be inputted into the bus repeatedly to optimize the effect of the compensation. Then, a proper damping resistor is selected and connected to the bus in series to absorb the energy of the surge. The signal compensation circuit is embedded in the chip, such as in the south bridge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.