Data storing method of dynamic RAM and semiconductor memory device
US7051260B2 · kind B2 · utility
31Cited by
10References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 9, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.