Systems and methods of routing data to facilitate error correction
US7051265B2 · kind B2 · utility
3Cited by
16References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacent bit pair domain. The adjacent bit pair domain data is transmitted over a bus having a plurality of data paths, such that data bits associated with a given memory device are transmitted over a same data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.