Method and apparatus for parallel carry chains
US7051296B1 · kind B1 · utility
7Cited by
9References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Apr 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.