Method and apparatus for detection and isolation during large scale circuit verification
US7051303B1 · kind B1 · utility
9Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jan 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing verification for a simulation design involves analyzing a simulation design using a testbench comprising a rapid bug detection tool, and if a bug is detected, adding a bug isolation tool to the testbench, and isolating and eliminating the bug using the testbench comprising the bug isolation tool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.