Delay estimation using edge specific miller capacitances
US7051305B1 · kind B1 · utility
2Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2004 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of estimating delay which includes configuring a first signal path and second signal path such that the first signal path is a victim signal path and the second signal path is an aggressor signal path, calculating Miller factors between the victim signal path and the aggressor signal path for a plurality of edge combinations between a victim signal edge and an aggressor signal edge, and using the Miller factors to perform a timing analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.