Autonomic graphical partitioning
US7051307B2 · kind B2 · utility
12Cited by
12References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Feb 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of desired number of logical blocks and repeats the process of identifying logical blocks for different hierarchical levels of the integrated circuit design until the number of logical blocks is within the range of the desired number of logical blocks. This serves as a guide to partition the chip as opposed to a grid-like partitioning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.