Method and apparatus for integrated circuit design with library cells
US7051308B2 · kind B2 · utility
4Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods are apparatuses are disclosed for library cells for designing an integrated circuit. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.