Automatic generation of programmable logic device architectures
US7051313B1 · kind B1 · utility
31Cited by
11References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | May 23, 2006 |
| Priority date | — |
| Expiry date | Nov 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An “architecture generation engine” is operative with a CAD system to implement circuits into PLD (programmable logic device) architectures and to evaluate performances of different architectures. The architecture generation engine converts a high level, easily specified description of a PLD architecture into a highly detailed, complete PLD architecture database that can be used by a CAD toolset to map a circuit netlist into a PLD. The architecture generation engine also enables performance evaluation of a wide variety of PLD architectures for given benchmark circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.