Method of manufacturing a semiconductor device having selective epitaxial silicon layer on contact pads
US7052983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2003 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Oct 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.