Track-and-hold peak detector circuit
US7053674B1 · kind B1 · utility
12Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Dec 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A track-and-hold peak detector circuit, which can operate at low input signal frequencies, includes a capacitor to hold a peak voltage of the input signal and logic circuitry that reduces an effect of leakage current into or out of the capacitor, and therefore, provides protection against self-switching of an output signal of the peak detector circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.