4X crystal frequency multiplier with op amp buffer between 2X multiplier stages
US7053725B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B19/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency-multiplying circuit generates a multiple of the fundamental frequency of a crystal that oscillates. A first differential multiplier is coupled to the crystal nodes and generates a frequency-doubled output. The frequency-doubled output is applied to an op amp that buffers the output and compares it to a reference to generate a pair of differential buffered signals. The differential buffered signals are applied to a second differential multiplier that generates a final quadrupled-frequency output. The differential multipliers can each have a pair of differential transistors that receive signals that oscillate out-of-phase to each other by 180 degrees. The drains of the differential transistors connect together at a summing node to sum the transistor currents, producing the frequency-doubled output. A crystal driver circuit using cross-coupled and direct-coupled transistors may also be attached to the crystal nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.