Personal computer system and core logic chip applied to same
US7053900B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2003 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A personal computer system includes a core logic unit, a graphics accelerator, a first tile converter, a local memory, a second tile converter and a system memory. The core logic unit outputs first image data in a linear mode. The graphics accelerator is in communication with the core logic unit for processing the first image data into second image data in a linear mode. The first tile converter is in communication with the graphics accelerator for converting the second image data into third image data in a tile mode. The local memory is in communication with the first tile converter for storing therein the third image data. The second tile converter is in communication with the core logic unit for converting the first image data into fourth image data in a tile mode. The system memory is accessible by the core logic unit, and includes a graphics accelerating memory in communication with the second tile converter for storing therein the fourth image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.