Logic-in-memory circuit using magnetoresistive element
US7054190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Aug 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A TMR network 120 using TMR elements as magnetoresistive elements is formed as a variable resistive element network by a series-parallel connection of two kinds of variable resistive elements R with resistance values that change according to an external input X or a memory input Y, as shown in an AND operation network 122 in FIG. 5(b), wherein the total resistance value Rtotal is minimized, that is, the current I is maximized for a particular combination of the inputs. Assuming Rxi and Ryi (i=0, 1 and 2) as the resistance values of the variable resistive elements R according, respectively, to the external input X and memory input Y, the values of x and y determine the current I that flows through the network as shown in FIG. 5(d). Setting a threshold value between I0 and I1 using a threshold detector 160 makes it possible to realize AND operation. The operation result is then output as a voltage value through an IV converter 170.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.