Serial memory address decoding scheme
US7054218B2 · kind B2 · utility
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12References
18Claims
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Assignee
Inventor
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Aug 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of pulses to the series of decoders in accordance with a difference in a stored previous address and a received current address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.