Semiconductor memory device
US7054223B2 · kind B2 · utility
18Cited by
2References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2004 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Aug 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.