Elimination of end-around-carry critical path in floating point add/subtract execution unit
US7054898B1 · kind B1 · utility
6Cited by
13References
4Claims
0Family size
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Key dates
| Filing date | Aug 4, 2000 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Feb 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry bit value calculator, to allow the correct rounding choice of the operands to be made before the mantissa portions of the operands are subtracted (added) rather than after.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.