Apparatus for use in a computer system
US7054969B1 · kind B1 · utility
5Cited by
16References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1999 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module being latency intolerant. The bus architecture comprises a primary bus (3) having latency intolerant modules connected thereto, a secondary bus (4) having latency tolerant modules connected thereto, and a primary to secondary bus interface module (5) interconnecting the primary and secondary buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.