Apparatus and method for dynamically enabling and disabling interrupt coalescing in data processing system
US7054972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for dynamically enabling and disabling interrupt coalescing in a data processing system. The present invention involves consistently monitoring IO load on an IOP of an IO adapter. The firmware on the IO adapter may have a global variable that stores counters for PCI function registers. Each counter tracks the number of outstanding IOs of a corresponding PCI function register. The counter is incremented whenever a new IO is received and is decremented upon posting the completed message back to the OS. A timer interrupt is generated periodically so that an ISR may be periodically performed. In the ISR, the maximum value stored of each counter seen since last timer interrupt is analyzed. When the maximum value stored is greater than a predetermined threshold value, the interrupt coalescing is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.