Bus interface for processor
US7054988B2 · kind B2 · utility
4Cited by
9References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 2003 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Feb 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus and configured to delay an access between the first bus and the second bus at least one pipeline cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.