Systems and processes for asymmetrically shrinking a VLSI layout
US7055114B2 · kind B2 · utility
4Cited by
4References
18Claims
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Key dates
| Filing date | Oct 8, 2003 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Jun 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processes, software and systems asymmetrically shrink a layout for a VLSI circuit design. A first VLSI circuit design layout, defined by a first fabrication process with first design rules, is asymmetrically scaled to a second VLSI circuit design layout defined by a second fabrication process with second design rules. Layouts of one or more leaf cells of the second VLSI circuit design layout are processed to ensure conformity to the second design rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.