Systems and methods for multi-tasking, resource sharing and execution of computer instructions
US7055151B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | May 30, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.