IC card
US7055752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2001 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | May 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/0723
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state control circuit gives an inactive state control signal to a CPU and an active state control signal to a data transmission circuit. In response to this, the CPU goes into the halt state and the data transmission circuit goes into the receive state. When receive processing is completed, the state control circuit gives an active state control signal to the CPU. In response to this, the CPU restores from the halt state to the operative state. The CPU gives an instruction signal to the state control circuit. The state control circuit gives an inactive state control signal to the data transmission circuit. In response to this, the data transmission circuit goes into the halt state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.