Methods of manufacturing a MOS transistor
US7056814B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Dec 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/608
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing MOS transistors which are capable of suppressing a short channel effect are disclosed. The short channel effect is suppressed by forming source/drain regions of a shallow junction and sufficiently doping a gate. An illustrated method includes: forming a gate insulating layer and a gate on a semiconductor substrate of a first conductivity type; forming lightly doped drain regions of a second conductivity type within the substrate at opposite sides of the gate; forming spacers on side walls of the gate; forming an insulating buffer layer; exposing a top surface of the gate by performing a planarization process on the insulating buffer layer; doping the gate by implanting impurity ions of the second conductivity type into the top surface of the gate; removing the insulating buffer layer; and forming source/drain regions of the second conductivity type within the substrate at opposite sides of the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.