Solid state imager with reduced number of transistors per pixel
US7057150B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/813
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid state imager with pixels arranged in columns and rows has the pixels are configured into groups of at least a first pixel and a second pixel, each said group sharing a pixel output transistor having a sense electrode and an output electrode and a reset transistor having a gate coupled to receive a reset signal and an output coupled to the sense electrode of the associated shared pixel output transistor. Each of the pixels has a photosensitive element whose output electrode is coupled to the sense electrode of the shared pixel output transistor and a gate electrode coupled to receive respective first and second pixel gating signals. This configuration reduces the number of FETs to two transistors for each pair of pixels, and also can achieve true correlated double sampling correction of FPN.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.