Semiconductor integrated circuit device having a test function
US7057948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Sep 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory collar, a repair data analyzer, a BIST block, and a system logic. The memory collar includes a memory cell and a spare cell and have a redundancy function of replacing fail memory cell with the spare cell if fail memory cell exists. The repair data analyzer determines whether or not memory cell included in the memory collar is defective, and generates fail address corresponding to the memory cell determined as being defective. The BIST block operates in synchrony with a first clock signal inputted to a first clock signal terminal in a test operation mode, and controls the operation of the memory collar. The system logic operates in synchrony with a second clock signal inputted to a second clock signal terminal in the test operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.