Semiconductor memory having mode register access in burst mode
US7057959B2 · kind B2 · utility
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Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.