Method and architecture for reducing the power consumption for memory devices in refresh operations
US7057960B1 · kind B1 · utility
77Cited by
29References
27Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.