Semiconductor integrated circuit device
US7057968B2 · kind B2 · utility
0Cited by
2References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 10, 2005 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.