Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices
US7058675B1 · kind B1 · utility
1Cited by
4References
18Claims
0Family size
Assignee
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Key dates
| Filing date | May 22, 2001 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2101/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. This approach is particularly applicable to circuits for calculating reciprocal values and circuits for performing normalized LMS algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.