EEPROM emulation in flash memory
US7058755B2 · kind B2 · utility
15Cited by
5References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient emulation of EEPROM employing flash memory employs a fixed location for an address pointer in flash memory and such that an erase operation is required only once every nth update where n is the number of bits at the fixed location, thus avoiding the need to erase the sector on every update and avoiding delays associated with linked lists for determining the address of the most up-to-date information. Use of bit shifting provides fast determination of the desired address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.