Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism
US7058782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2003 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.