Techniques for programming and verifying data in a programmable circuit
US7058880B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2001 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | May 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes techniques for programming and verifying data in a programmable circuit. Programmable circuits such as PLDs may include a plurality of rows and columns of memory cells. Data is programmed into memory elements associated with the rows and columns. Subsequently, the programmed data may be extracted for verification. A first word line may be selected by first word line address bits in row shift registers. Data programmed into the first word line is loaded into column shift registers for verification during one or more verify steps. During a program step, data is programmed into memory elements in a second word line that is selected by the first word line address bits. The present invention also provides a technique for shifting program data bits into the column shift registers at the same time that verify data bits are shifted out of the column shift registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.