Reduction of cross-talk noise in VLSI circuits
US7058907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2004 |
| Grant date | Jun 6, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A process for reducing cross-talk noise in a VLSI circuit is disclosed. The process identifies a victim net in an integrated circuit and calculates a change in ground capacitance for the victim net to identify a noise amplitude less than or equal to a maximum allowable noise height. The process selects from a library one cell or a grouping of cells having an input capacitance for the victim net closest to the change in ground capacitance. The selected cell or grouping of cells is coupled to the victim net so that its change in ground capacitance provides a noise amplitude less than (or less than or equal to) an allowable maximum noise height that may be a predetermined value. A system for reducing cross-talk noise in a VLSI circuit is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.