Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
US7061055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Jan 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.