Semiconductor device, stacked semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US7061118B2 · kind B2 · utility
16Cited by
3References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 3, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | May 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/07811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having a connection terminal and a substrate on which a circuit section and an electrode are stacked in this order, the circuit section having a multilayer interconnect structure, the electrode being conductively connected to the circuit section, and the connection terminal penetrating the substrate and being conductively connected to the electrode. Part of the connection terminal is formed simultaneously with an interconnect in an interconnect layer of the circuit section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.