Semiconductor package with pattern leads and method for manufacturing the same
US7061125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2003 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Mar 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package utilizing insulating peripheral sealing portions and pattern leads and methods for manufacturing such semiconductor packages are provided. The semiconductor package includes a substrate on which a semiconductor chip is mounted. The substrate includes a plurality of substrate pads and the semiconductor chip includes a plurality of chip pads on an active surface. The semiconductor chip is surrounded by one or more peripheral sealing layers and conductive lead patterns are formed across the peripheral sealing layer(s) to connect the chip pads to corresponding substrate pads. The chip and lead patterns may be encapsulated and the substrate may also be provided with external connection structures such as solder balls to complete the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.