Circuit for maintaining hold-up time while reducing bulk capacitor size and improving efficiency in a power supply
US7061212B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2004 |
| Grant date | Jun 13, 2006 |
| Priority date | — |
| Expiry date | Aug 6, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit that utilizes most of the energy stored in the bulk capacitor of an AC to DC or DC to DC converter power supply by providing an intermediate converter between a first stage boost converter and a DC-DC converter. When the bulk voltage starts to fall during the hold-up time, the intermediate converter boosts the falling voltage to maintain the regulated DC input to the DC to DC converter while reducing the operating range and increasing the operating duty cycle, so as to increase efficiency, reduce peak current and voltage stresses. The circuit also reduces the size of the output filter components and reduces the size of the bulk capacitance by up to half.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.